Analog-to-digital converters (ADCs) are used to convert an unknown input voltage into a digital representation. Most ADCs work discretely. Among the discrete time ADCs, the pipeline ADCs and Delta-Sigma ADCs operate in a time division configuration including a sampling phase and an integration phase.
During the sampling phase, the integrator in the ADC will sample the input voltage. During the integrating phase, the ADC integrates or amplifies and then compares the result with a reference voltage. The unknown input voltage is applied to the input of the integrator and allowed to ramp for a fixed time period. Then a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero. The input voltage is computed as a function of the reference voltage, the constant run-up time period, and the measured run-down time period.
The sampling time and integrating time for the integrator circuit are controlled by two non-overlapping clocks. The clock source is typically from a local oscillator having a fixed 50% duty cycle. While the pulse widths of the two clocks are the same, the time constants of the sampling phase clock and the integrating phase clock are not the same. The integrating phase typically has a larger time constant since it is determined by the input transconductance of an amplifier of the integrator and the integrating capacitance. The input transconductance is limited and the time constant of the sampling phase is determined by a sampling switch resistance and sampling capacitance. The resistance is usually relatively small.
In designing the amplifier for the integrator, the time constant should be 1/N of the pulse width of the integrating phase. Such a time constant enables the settling accuracy to be N*τ where τ is the time constant and the settling accuracy of N*τ means an accuracy of e−N. If N=7, the settling accuracy is 0.09%. However, since the amplifier has process limitations in slow skew, the transconductance of the amplifier is smaller than a typical value. Thus, the time constant turns out to be larger than 1/N of the pulse width and the settling accuracy is reduced. The amplifier current may be increased to compensate for the inaccuracy but then the ADC power usage also increases.